`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:26:15 05/24/2013 
// Design Name: 
// Module Name:    SevenSeg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module SevenSeg(
    input clk,
	 input [3:0]digitOn,
    input [3:0]dis1,
    input [3:0]dis2,
    input [3:0]dis3,
    input [3:0]dis4,
	 input [3:0]dot,
	 output [6:0]seg,
	 output dp,
	 output [3:0]an
    );
	 
	 reg [13:0] count;//14
	 reg [1:0] select;
	 
	 always @(posedge clk) begin
		if(count == 14'b0) select  <= select + 2'b1;
		else select <= select;
		count <= count + 14'b1;
	 end
	 
	 reg enableDigit;
	 
	 reg [3:0] selectedData;
	 reg [3:0] anReg;
	 always @(*) begin
		case(select)
			2'd0: selectedData = dis1;
			2'd1: selectedData = dis2;
			2'd2: selectedData = dis3;
			2'd3: selectedData = dis4;
		endcase
		case(select)
			2'd0: anReg = 4'b1110;
			2'd1: anReg = 4'b1101;
			2'd2: anReg = 4'b1011;
			2'd3: anReg = 4'b0111;
		endcase
		case(select)
			2'd0: enableDigit = digitOn[0];
			2'd1: enableDigit = digitOn[1];
			2'd2: enableDigit = digitOn[2];
			2'd3: enableDigit = digitOn[3];
		endcase
	 end
	 
	 assign an = anReg;
	 assign dp = ~(|(dot & ~anReg));
	 
	 reg [6:0] segReg;
	 assign seg = enableDigit ? segReg : 7'b1111111;
	 
	 always @(*) begin
		case(selectedData)
			4'h0: segReg = 7'b1000000;
			4'h1: segReg = 7'b1111001;
			4'h2: segReg = 7'b0100100;
			4'h3: segReg = 7'b0110000;
			4'h4: segReg = 7'b0011001;
			4'h5: segReg = 7'b0010010;
			4'h6: segReg = 7'b0000010;
			4'h7: segReg = 7'b1111000;
			4'h8: segReg = 7'b0000000;
			4'h9: segReg = 7'b0011000;
			4'hA: segReg = 7'b0001000;
			4'hB: segReg = 7'b0000011;
			4'hC: segReg = 7'b1000110;
			4'hD: segReg = 7'b0100001;
			4'hE: segReg = 7'b0000110;
			4'hF: segReg = 7'b0001110;
		endcase
		
	 
	 end
endmodule
